1. Field of the Invention
The present invention relates to the field of computer systems and, more particularly to a high speed bus topology for expandable computer systems.
2. Description of the Related Art
Today's computer and network systems require the ability to expand their hardware over time to improve their performance or to accommodate new users. Expansion capabilities are typically provided for graphics, input/output (I/O), network interface, microprocessors, static random access memory (SRAM) and dynamic random access memory (DRAM) circuit cards. These expansion cards are typically integrated on a printed circuit board (PCB) that can easily be inserted or removed by a user of the system. The PCB is inserted into a connector, which provides an electrical connection to a bus.
The expandable bus is typically located on a host PCB, often referred to as a motherboard. Connectors are mounted on the motherboard to provide slots for hardware expansion. The bus connects to the expansion card through the connector. Expansion cards are also known as add-in cards. This connection typically results in a branch off the main bus to the receiving components on the expansion card. This branch is commonly referred to as a stub connection. The stubs are electrically undesirable for high-speed buses, since they provide a discontinuity of impedance along the bus, which results in reflected energy on the bus.
One technique that has been used to reduce the effect of stubs on the bus includes the use of series resistors on the add-in cards. This technique isolates the stubs from the main bus and the resistors help dissipate the energy of the reflected waves travelling within the stub. FIG. 1 illustrates a conventional high speed bus system 10, typically used in network switches, hubs and computer systems, utilizing the series resistor technique. This system 10 is often referred to as a stub bus system. For the purposes of this discussion, the system 10 will represent a computer main memory subsystem. It should be noted that this is just an example and that the same system 10 is appropriate for any high-speed bus having removable circuit cards.
The system 10 includes two circuit cards 30, 40 that are attached to bus lines B1, B2, B3, B4 through connectors 14, 16, respectively. The point where the bus lines B1, B2, B3, B4 branch off into the connectors are the stub connection points S1, S2, S3, S4, S5, S6, S7, S8 (collectively referred to herein as stub connections S). The bus lines B1, B2, B3, B4 may comprise the main computer bus B for the system 10 or a sub-bus. Each bus line B1, B2, B3, B4 may be a 16-bit wide bus line, making the bus B a 64-bit bus. A memory controller 12 is connected to the bus lines B1, B2, B3, B4 and manages data flow on the bus B. The controller 12, bus lines B1, B2, B3, B4 and connectors 14, 16 all reside on the computer motherboard M. The circuit cards 30, 40 contain circuit elements 32, 42, respectively, which for this example are memory chips. Each bus line B1, B2, B3, B4 is terminated by termination resistors 20, 22, 24, 26, respectively.
In the present example, each connector 30, 40 (also referred to as a slot) is provided for increasing the memory storage capacity of the system 10. Although only two connectors 14, 16 are illustrated, there can be any number of connectors 14, 16. Typically, the number of slots will be determined by the maximum bus B operating frequency or by the maximum desired memory capacity. In the present example, the connectors 14, 16 can be 184-pin dual in-line memory module (DIMM) connectors and the cards 30, 40 can be double data rate (DDR) synchronous DRAM (SDRAM) modules.
The termination resistors 20, 22, 24, 26 are provided for high-speed signal termination of the bus B. Each resistor 20, 22, 24, 26 has a value that is normally chosen to be equal to the loaded characteristic impedance of the bus system 10. Termination of the bus B prevents signal reflections that result from a mismatch in impedance at the end of the bus B.
Series or stub resistors 34, 44 are included in each card 30, 40, respectively, at a point near the interface to the connectors 14, 26 (i.e., near the stub points S1, S2, S3, S4, S5, S6, S7, S8). The stub resistors 34, 44 serve two purposes related to improving the signal integrity and increasing the bandwidth of the system 10. First, the resistors 34, 44 help increase the impedance of the stub connections and therefore, isolate the stubs from the main motherboard bus. Second, the resistors 34, 44 help attenuate the reflected energy that travels up and down the stubs from the motherboard to the main memory bus.
The use of stub resistors 34, 44 is quite effective for reducing reflections and improving the operating bandwidth, but there are some drawbacks. There is some added system cost and module layout complexity associated with the large number of resistors. In a DDR SDRAM DIMM, for example, the data bus width can be 64 or 72 bits wide. Since there is termination at the end of the bus, there becomes a DC path for current from the DRAM driving the bus, through the stub resistor, into a parallel resistor and into a termination voltage (typically referred to as VTT). The stub resistor reduces the voltage swing of the signal on the bus, so it is necessary to reduce the driver impedance or to increase the output driver supply voltage on the DRAM (typically referred to as VDDQ). Reducing the drive impedance requires a larger device, which increases the input/output capacitance of the DRAM. The higher capacitance has the effect of reducing bus bandwidth, so typically, a larger VDDQ is used to increase the voltage swing to the appropriate level.
Another technique to reduce the effects of stubs on the bus is to remove the stub connection points. FIG. 2 illustrates a system 50 where the bus B is looped through a connector 54, circuit card 60 and then back out the same connector 54. The bus B is then looped through a second connector 56, circuit card 70 and then back out the same connector 56 where it is terminated by a termination resistor 58. This system 50 is often referred to as a loop-through bus system. Keeping with the above example illustrated in FIG. 1, the system 50 is a computer main memory subsystem. The system includes a memory controller 52 that is mounted on the computer motherboard M along with the bus B, connectors 54, 56 and resistor 58. Each card 60, 70 contains circuit elements 62, 72, respectively, which for this example are memory chips. The bus B may be a 16-bit bus.
By eliminating the stub connections, the loop-through bus system improves the operating bandwidth, provided that a uniform transmission line impedance is maintained throughout all sections of the bus B. This requires that the impedance of the connectors 54, 56 match the bus trace impedance. It also means that the sections of the cards 60, 70 that are populated by the elements 62, 72 must have the same loaded characteristic impedance as sections without the elements 62, 72. A typical motherboard PCB bus line impedance will be around 60 ohms for a minimum width line. However, in the section where the DRAM devices are located, there is an increase in capacitance per unit length due to the DRAM input capacitance. Therefore, the effective impedance of the bus is reduced.
In the populated section of the card, a loaded impedance of 25 to 30 ohms is typical. In order to achieve a uniform bus impedance, it is necessary to increase the line widths of the bus in the unpopulated sections so that its impedance is equal to the impedance of the populated sections. This layout restriction becomes impractical for larger bus widths due to the congestion of the bus and due to the amount of board surface area that the bus uses. Further, the lower bus impedance requires a lower termination resistance, which dissipates more power for a given signal voltage swing.
Another disadvantage of the loop-through system 50 is that the bus length gets very long. The longer bus length results in an increase in propagation delay from when the controller 52 drives the bus B until the information is received at the elements 62, 72 (a DRAM element in this example). This is often referred to as flight time. The longer flight time increases the latency from when the controller 52 requests information until the information is received at the controller 52. The increased latency reduces the computer system performance. Longer flight times can also reduce the efficiency of the bus B for moving information. Typically, there is a brief waiting period that occurs between one device releasing the bus B and a different device driving the bus B. The waiting period is necessary to allow the data to propagate to one end of the bus and/or to allow the bus voltage to settle to a stable state. In the case of a DRAM element 62, 72 (hereinafter referred to as a “DRAM element”) driving the bus B followed by the controller 52 driving the bus B, the controller 52 must wait until the previous data is received at the controller 52 before it turns on its driver. Otherwise, the data will be corrupted.
A similar waiting period can occur when one DRAM element releases the bus B before another DRAM element drives the bus B. If there is an existing voltage waveform propagating on the bus B this situation can result in excessively high or low voltages on the bus B when the second DRAM element drives it. Since it is not practical to for the bus B to maintain a perfectly uniform impedance, there will also be some reflected energy travelling along the bus B. If the bus B voltage is not in a stable state when the next DRAM element drives it, the transition time of the signal moving through the reference voltage will be adversely effected. This results in an increase or decrease in the delay of the recognition of a logical one or zero voltage. This delay change results in timing uncertainty or timing errors, which can corrupt the data that is latched into the receiving device. This is a form of inter-symbol interference where the previous data value can effect the capture of the next data bit or symbol.
Another disadvantage of the long bus B of the loop-through bus system 50 is a reduction in maximum operating bandwidth. Since the bus B is not physically ideal, there is attenuation and dielectric leakage in the PCB. These losses result in a reduction of signal swing and get worse at higher frequencies. Since there also is reflected energy travelling along the bus B, the rate at which data can be transmitted on the bus B becomes limited.
A further disadvantage of the loop-through bus system 50 is that its long bus B can increase the electromagnetic interference (EMI) of the system 50. EMI increases as the cross-sectional area of a signal and its ground return path are increased. In the current example, a signal transmitted from the controller 52 will travel down the bus B. The signal's electromagnetic wave return path will predominately be along the ground plane located under the signal. In a personal computer (PC) system, the memory cards are typically 5.25 inches wide by 1.25 inches tall. This means that the length of the bus routed through the memory card is over 6 inches. For a three card system, the total bus length can be over 20 inches. This provides ample opportunities for EMI and signal attenuation.
Accordingly, there is a desire and need for a high-speed bus topology for expandable computer systems that provides a relatively shorter bus having a substantially greater operating bandwidth of the bus while maintaining a uniform transmission line impedance.